1. Field of the Invention
This invention relates to a process for making integrated circuit structures. More particularly, this invention relates to a chemical mechanical polishing (CMP) process for removing excess metal deposited on an oxide layer of an integrated circuit structure during the filling of trenches and/or vias with metal wherein a dielectric etch stop layer is formed over the oxide layer to prevent erosion of the oxide layer during the CMP process.
2. Description of the Related Art
When vias formed in silicon oxide dielectric layers are filled with metal, typically a layer of the metal (or a composite of multiple conductive layers) is deposited on the surface of the oxide dielectric layer. The deposited metal layer fills up the vias as it deposit on the oxide dielectric layer. Similarly, when a trench is filled with metal, in a damascene or double damascene process, a layer of the metal is deposited on the surface of the oxide dielectric layer in which the trench is formed to fill up the trench with metal as the metal deposits on the oxide dielectric layer.
Subsequently the portions of the metal layer on the surface of the oxide dielectric layer are removed by some type of planarizing or polishing process leaving a planarized surface with the metal only in the trenches and/or vias. This idealized situation is shown in prior art FIGS. 1 and 2. In FIG. 1 a silicon oxide dielectric layer 10 is shown formed over underlying portions of an integrated circuit structure 2. Vias, contact openings, and/or trenches 14, previously formed in oxide dielectric layer 10 are, for simplicity sake, shown filled with a single layer of metal 20, e.g., aluminum, which has been deposited over the surface of oxide dielectric layer 10.
As shown in prior art FIG. 2, when the structure of FIG. 1 is subjected to a planarizing step such as a chemical mechanical polishing (CMP) step to remove the excess metal on the surface of the oxide dielectric layer the theoretical result should be the highly planarized structure shown in FIG. 2. All metal is removed from the upper surface of oxide dielectric layer 10, and metal 20 remains only in trenches and/or vias 14, with the upper surface of the metal 20 in trenches and/or vias 14 forming a highly planar surface with the surface of the oxide dielectric layer. The CMP process used is intended to be highly selective to the oxide dielectric material with respect to the metal (i.e., the metal is supposed to be etched and removed by the process at a much faster rate than the oxide dielectric material), thus removing only the excess metal, and leaving the planarized structure shown in FIG. 2.
Unfortunately, this idealized highly planar structure does not always result from use of a CMP process, particularly when the trenches and/or vias are closely spaced apart. Prior art FIGS. 3 and 4 illustrate the problem. In FIG. 3, trenches and/or vias 16 are shown closely spaced apart, in oxide dielectric layer 10. Metal layer 20 is again shown as deposited over oxide dielectric layer 10 to fill trenches and/or vias 14 and 16. However, when the structure of FIG. 3 is subjected to the previously described CMP process to remove the excess surface portions of metal layer 20, some of the oxide dielectric material in between the closely spaced apart metal-filled trenches and/or vias 16 is also removed with the metal. This results in the structure shown in prior art FIG. 4, with eroded oxide portions 18 in between eroded trenches and/or vias 16xe2x80x2, with the metal filling 20xe2x80x2 in trenches and/or vias 16xe2x80x2 also partially eroded away as well, leaving concave surfaces in the regions where the trenches and/or vias are closely spaced apart.
It would be advantageous to be able to planarize the structures of both FIGS. 1 and 3 in a manner which would remove all of the portions of metal layer 20 on the surface of oxide dielectric layer 14, to achieve the highly planarized profile of FIG. 2, even when the trenches and/or vias are closely spaced apart as in FIGS. 3 and 4.
In Weidan Li et al. Ser. No, 09/425,552, entitled INTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINES, filed on Oct. 22, 1999 and assigned to the assignee of this application, and the subject matter of which is hereby incorporated by references, one of us, with others, suggested the use of a silicon oxynitride capping layer over metal lines to provide an antireflective coating which could also function as a etch stop layer for a CMP planarizing process. However, this process did not protect oxide from a CMP step being used to remove metal, but rather protected metal against a CMP process being used to remove oxide. Neither was the described process for removing oxide over the silicon oxynitride on metal lines intended to solve a problem with respect to formation of concave portions of the metal/oxide surface during the polishing step.
It would, therefore, be desirable to be able to remove all of the excess metal from the surface of an oxide dielectric layer having closely spaced apart metal-filled trenches and/or vias therein while inhibiting the formation of concave portions in the surface of the oxide dielectric layer during a CMP step used to remove the excess metal.
In accordance with the invention a process is provided for planarizing an integrated circuit structure by chemical mechanical polishing (CMP) after filling, with at least one metal, a plurality of trenches and/or vias formed in a silicon oxide layer on the integrated circuit structure. The process, which is capable of inhibiting formation of concave surface portions on the silicon oxide surface, during the CMP process, in regions where the trenches and/or vias are closely spaced apart, comprises forming, over a layer of silicon oxide of an integrated circuit structure, an antireflective coating (ARC) layer of dielectric material capable of functioning as an etch stop layer in a CMP process to remove metal; and using this ARC layer as an etch stop layer to assist in removal of excess metal used to fill the trenches and/or vias formed in the oxide layer.
The particular material chosen for the ARC layer should have a lower etch rate, in a CMP process, than does the underlying oxide dielectric layer. Trenches and/or vias are then formed through the ARC layer and the oxide dielectric layer. These trenches and/or vias are then filled with conductive material, such as at least one metal layer, by depositing at least one such metal layer over the ARC layer. Excess trench and/or via filler metal is then removed from the top surface of the ARC layer by subjecting the metal to a CMP step which is selective to the ARC layer, thereby permitting the ARC layer to function as a stop layer which protects the underlying oxide dielectric layer from exposure to the CMP process. Since the ARC layer has a lower etch rate, in the CMP process, than does the oxide dielectric layer, the formation of dished and/or concave regions in the surface is inhibited, including those regions where the trenches and/or vias are closely spaced apart.